Chang Meng  孟畅


       Postdoctoral researcher at Integrated Systems Laboratory (LSI)
       École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
       Email: chang.meng@epfl.ch
       [Github]   [Google scholar]

[Biography] [Open-source Codes] [Publications] [Professional Activities] [Major Awards]

Biography    [back top]

    I am a postdoctoral researcher at the Integrated Systems Laboratory (LSI) of EPFL. I am fortunate to work with Prof. Giovanni De Micheli. I received my Ph.D. degree in 2023 from Shanghai Jiao Tong University, where I was fortunate to be supervised by Prof. Weikang Qian. I study electronic design automation (EDA). My research interests lie in logic synthesis, verification, and applications for emerging computing paradigms, such as approximate computing.

Open-source Codes   [back top]

Publications   [back top]

Conference Papers

C015. Chang Meng, Wayne Burleson, Weikang Qian, and Giovanni De Micheli
Gradient approximation of approximate multipliers for high-accuracy deep neural network retraining
To appear in Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, 2025.
Acceptance rate: 25%.
C014. Chang Meng✉, Mingfei Yu, Hanyu Wang, Wayne Burleson, and Giovanni De Micheli
RareLS: Rarity-reducing logic synthesis for mitigating hardware trojan threats
In International Conference on Computer-Aided Design (ICCAD), New Jersey, USA, 2024.
Acceptance rate: 24.0%.
C013. Toshiaki Koike-Akino, Chang Meng✉, Volkan Cevher and Giovanni De Micheli
Hardware-efficient quantization for green custom foundation models
In International Conference on Machine Learning (ICML) Workshop, Vienna, Austria, 2024.
C012. Hanyu Wang, Chang Meng✉, and Giovanni De Micheli
Global crossover: An evolution strategy for logic synthesis
In International Workshop on Logic and Synthesis (IWLS), Zurich, Switzerland, 2024.
C011. Chang Meng, Hanyu Wang, Yuqi Mai, Weikang Qian✉, and Giovanni De Micheli✉
VECSEM: Verifying average errors in approximate circuits using simulation-enhanced model counting [pdf] [code]
Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024.
Best Paper Nomination. Acceptance rate: 25%.
C010. Xuan Wang, Zheyu Yan, Chang Meng, Yiyu Shi, and Weikang Qian✉
DASALS: Differentiable architecture search-driven approximate logic synthesis [pdf]
International Conference on Computer Aided Design (ICCAD), San Francisco, USA, 2023.
Acceptance rate: 22.9%.
C009. Chang Meng, Jiajun Sun, Yuqi Mai, and Weikang Qian✉
MECALS: A maximum error checking technique for approximate logic synthesis [pdf] [code]
Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023.
Acceptance rate: 25%.
C008. Xingyue Qian, Chang Meng, Xiaolong Shen, Junfeng Zhao, Leibin Ni, and Weikang Qian✉
High-accuracy low-power reconfigurable architectures for decomposition-based approximate lookup table [pdf]
Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023.
C007. Chang Meng$, Xuan Wang$, Jiajun Sun, Sijun Tao, Wei Wu, Zhizhang Wu, Leibin Ni, Xiaolong Shen, Junfeng Zhao, and Weikang Qian✉ ($equal contribution)
SEALS: Sensitivity-driven efficient approximate logic synthesis [pdf]
Design Automation Conference (DAC), San Francisco, CA, USA, 2022.
Acceptance rate: 23%.
C006. Chang Meng, Zhiyuan Xiang, Niyiqiu Liu, Yixuan Hu, Jiahao Song, Runsheng Wang, Ru Huang, & Weikang Qian✉
DALTA: A decomposition-based approximate lookup table architecture [pdf]
International Conference on Computer-Aided Design (ICCAD), Munich, Germany, 2021.
Acceptance rate: 23.5%.
C005. Yifan Qian, Chang Meng, Yawen Zhang, Weikang Qian✉, Runsheng Wang, and Ru Huang
Approximate logic synthesis in the loop for designing low-power neural network accelerator [pdf]
International Symposium on Circuits and Systems (ISCAS), Daegu, South Korea, 2021.
C004. Zuodong Zhang, Runsheng Wang, Zhe Zhang, Ru Huang, Chang Meng, Weikang Qian, and Zhuangzhuang Zhou,
Reliability-enhanced circuit design flow based on approximate logic synthesis [pdf]
Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, 2020.
C003. Chang Meng, Weikang Qian✉, and Alan Mishchenko
ALSRAC: Approximate logic synthesis by resubstitution with approximate care set [pdf] [code]
Design Automation Conference (DAC), San Francisco, CA, USA, 2020.
Acceptance rate: 23.2%.
C002. Chang Meng, Paul Weng, Sanbao Su, and Weikang Qian✉
Advanced ordering search for multi-level approximate logic synthesis [pdf]
International Workshop on Logic and Synthesis (IWLS), Lausanne, Switzerland, 2019.
C001. Zhuangzhuang Zhou, Yue Yao, Shuyang Huang, Sanbao Su, Chang Meng, and Weikang Qian✉
DALS: Delay-driven approximate logic synthesis [pdf]
International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, 2018.

Journal Papers

J003. Chang Meng, Alan Mishchenko, Weikang Qian✉, and Giovanni De Micheli
Efficient resubstitution-based approximate logic synthesis
To appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
J002. Chang Meng, Zhuangzhuang Zhou, Yue Yao, Shuyang Huang, Yuhang Chen, and Weikang Qian✉
HEDALS: Highly efficient delay-driven approximate logic synthesis [pdf] [code]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.
J001. Sanbao Su$, Chang Meng$, Fan Yang, Xiaolong Shen, Leibin Ni, Wei Wu, Zhihang Wu, Junfeng Zhao, and Weikang Qian✉ ($equal contribution)
VECBEE: A versatile efficiency-accuracy configurable batch error estimation method for greedy approximate logic synthesis [pdf] [code]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.

Professional Activities   [back top]

Major Awards   [back top]