Biography
I am an Assistant Professor at the Department of Mathematics and Computer Science at Eindhoven University of Technology (TU/e). From 2023 to 2025, I was a postdoctoral researcher at the Integrated Systems Laboratory (LSI) of EPFL, where I was fortunate to work with Prof. Giovanni De Micheli. I received my Ph.D. degree in 2023 from Shanghai Jiao Tong University, supervised by Prof. Weikang Qian. I study electronic design automation (EDA), specifically on logic synthesis and verification, approximate computing, and AI accelerators.
Publications
Many publications have OPEN SOURCE codes. Play with them and let me know if you have any questions or suggestions.Conference Papers
| Chang Meng, Hanyu Wang, Yuyang Ye, Mingfei Yu, Wayne Burleson and Giovanni De Micheli.
TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators To appear in Design Automation Conference (DAC), Long Beach, USA, 2026. |
| Yuyang Ye, Xiangfei Hu, Leyun Tian, Chang Meng, Qing He and Longxing Shi
Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse To appear in Design Automation Conference (DAC), Long Beach, USA, 2026. |
| Jian Shi, Xuan Wang, Chang Meng, and Weikang Qian✉.
QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs [pdf] [code] In International Workshop on Logic Synthesis (IWLS), Verona, Italy, 2025. Best Student Paper Award. |
| Andrea Costamagna✉, Chang Meng, and Giovanni De Micheli.
SPFD-based delay resynthesis [pdf] In International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), Istanbul, Turkey, 2025. Best Paper Award. |
| Chang Meng✉, Wayne Burleson, Weikang Qian, and Giovanni De Micheli
Gradient approximation of approximate multipliers for high-accuracy deep neural network retraining [pdf] [code] In Design, Automation & Test in Europe Conference & Exhibition (DATE), Lyon, France, 2025. Acceptance rate: 25%. |
| Chang Meng✉, Mingfei Yu, Hanyu Wang, Wayne Burleson, and Giovanni De Micheli
RareLS: Rarity-reducing logic synthesis for mitigating hardware trojan threats [pdf] [code] In International Conference on Computer-Aided Design (ICCAD), New Jersey, USA, 2024. Acceptance rate: 24.0%. |
| Toshiaki Koike-Akino✉, Chang Meng, Volkan Cevher and Giovanni De Micheli
Hardware-efficient quantization for green custom foundation models In International Conference on Machine Learning (ICML) Workshop, Vienna, Austria, 2024. |
| Hanyu Wang, Chang Meng, and Giovanni De Micheli
Global crossover: An evolution strategy for logic synthesis In International Workshop on Logic and Synthesis (IWLS), Zurich, Switzerland, 2024. |
| Chang Meng, Hanyu Wang, Yuqi Mai, Weikang Qian✉, and Giovanni De Micheli✉
VECSEM: Verifying average errors in approximate circuits using simulation-enhanced model counting [pdf] [code] Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024. Best Paper Nomination. Acceptance rate: 25%. |
| Xuan Wang, Zheyu Yan, Chang Meng, Yiyu Shi, and Weikang Qian✉
DASALS: Differentiable architecture search-driven approximate logic synthesis [pdf] International Conference on Computer Aided Design (ICCAD), San Francisco, USA, 2023. Acceptance rate: 22.9%. |
| Chang Meng, Jiajun Sun, Yuqi Mai, and Weikang Qian✉
MECALS: A maximum error checking technique for approximate logic synthesis [pdf] [code] Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023. Acceptance rate: 25%. |
| Xingyue Qian, Chang Meng, Xiaolong Shen, Junfeng Zhao, Leibin Ni, and Weikang Qian✉
High-accuracy low-power reconfigurable architectures for decomposition-based approximate lookup table [pdf] Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023. |
| Chang Meng$, Xuan Wang$, Jiajun Sun, Sijun Tao, Wei Wu, Zhizhang Wu, Leibin Ni, Xiaolong Shen, Junfeng Zhao, and Weikang Qian✉ ($equal contribution)
SEALS: Sensitivity-driven efficient approximate logic synthesis [pdf] Design Automation Conference (DAC), San Francisco, CA, USA, 2022. Acceptance rate: 23%. |
| Chang Meng, Zhiyuan Xiang, Niyiqiu Liu, Yixuan Hu, Jiahao Song, Runsheng Wang, Ru Huang, & Weikang Qian✉
DALTA: A decomposition-based approximate lookup table architecture [pdf] International Conference on Computer-Aided Design (ICCAD), Munich, Germany, 2021. Acceptance rate: 23.5%. |
| Yifan Qian, Chang Meng, Yawen Zhang, Weikang Qian✉, Runsheng Wang, and Ru Huang
Approximate logic synthesis in the loop for designing low-power neural network accelerator [pdf] International Symposium on Circuits and Systems (ISCAS), Daegu, South Korea, 2021. |
| Zuodong Zhang, Runsheng Wang, Zhe Zhang, Ru Huang, Chang Meng, Weikang Qian, and Zhuangzhuang Zhou,
Reliability-enhanced circuit design flow based on approximate logic synthesis [pdf] Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, 2020. |
| Chang Meng, Weikang Qian✉, and Alan Mishchenko
ALSRAC: Approximate logic synthesis by resubstitution with approximate care set [pdf] [code] Design Automation Conference (DAC), San Francisco, CA, USA, 2020. Acceptance rate: 23.2%. |
| Chang Meng, Paul Weng, Sanbao Su, and Weikang Qian✉
Advanced ordering search for multi-level approximate logic synthesis [pdf] International Workshop on Logic and Synthesis (IWLS), Lausanne, Switzerland, 2019. |
| Zhuangzhuang Zhou, Yue Yao, Shuyang Huang, Sanbao Su, Chang Meng, and Weikang Qian✉
DALS: Delay-driven approximate logic synthesis [pdf] International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, 2018. |
Journal Papers
| Chang Meng✉, Weikang Qian, and Giovanni De Micheli
Simulation-guided approximate logic synthesis under the maximum error constraint [pdf] [code] In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026. |
| Chang Meng, Alan Mishchenko, Weikang Qian✉, and Giovanni De Micheli
Efficient resubstitution-based approximate logic synthesis [pdf] [code] In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025. |
| Chang Meng, Zhuangzhuang Zhou, Yue Yao, Shuyang Huang, Yuhang Chen, and Weikang Qian✉
HEDALS: Highly efficient delay-driven approximate logic synthesis [pdf] [code] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. |
| Sanbao Su$, Chang Meng$, Fan Yang, Xiaolong Shen, Leibin Ni, Wei Wu, Zhihang Wu, Junfeng Zhao, and Weikang Qian✉ ($equal contribution)
VECBEE: A versatile efficiency-accuracy configurable batch error estimation method for greedy approximate logic synthesis [pdf] [code] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. |
Professional Services
- Conference TPC Member:
- ICCD'26, EDA track
- ICCAD'26, high-level_and_logic_synthesis
- DAC'26, high-level synthesis and logic synthesis track
- DATE'26, approximate computing track
- ICCD'25, EDA track
- ICCAD'25, high-level synthesis and logic synthesis track
- DATE'25, approximate computing track
- DAC'25, high-level synthesis and logic synthesis track
- ISEDA'25
- IWLS'25
- GLSVLSI'24
- ITC-Asia'24
- Conference Organizing Committee:
- FPL'26, Collaborative Projects Event Co-Chair
- Journal Reviewer: TCAD, TODAES, TVLSI, TCAS-I, TNANO, Integration, and Microeletronics Journal
Awards
- Best Paper Award (co-author), International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD), 2025
- Member of Distinguished Review Board, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025
- Best Student Paper Award (co-author), International Workshop on Logic Synthesis, 2025
- Outstanding Reviewer Award, Design, Automation & Test in Europe Conference & Exhibition, 2025
- Best Paper Nomination, Design, Automation & Test in Europe Conference & Exhibition, 2024
- Best Ph.D. Dissertation Award, China EDA Ecosystem Development Accelerator, 2023
- A. Richard Newton Young Student Fellow Program Attendee, 2020
- Runner-up, International Workshop on Logic Synthesis (IWLS) Programming Contest, 2019
- National Scholarship (B.S.), Ministry of Education of China, 2015
Teaching
- 2ICS00 Bachelor Final Project, TU/e, Q3-Q4 2026
- CS472 Design Technologies for Integrated Systems (English), Teaching Assistant (Co-Lecturer), EPFL, Fall 2024
- VG501 Technical Communication, Teaching Assistant, SJTU, Fall 2020
- VE527 Computer-Aided Design of Integrated Circuits, Teaching Assistant, SJTU, Fall 2019
Talks
- Low-Power Design with Approximate Computing: Synthesis, Verification and AI Application
UMass Amherst, Amherst, USA, Nov. 2024
New York University, New York, USA, Nov. 2024
Shanghai Jiao Tong University, Shanghai, China, Dec. 2024
Hunan University, Changsha, China, Jan. 2025 - Approximate Computing for Energy-Efficient Circuits and AI Accelerators, TU Darmstadt, Darmstadt, Germany, Oct. 2025