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Chang Meng 孟畅Postdoctoral researcher at Integrated Systems Laboratory (LSI) École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland Email: chang.meng@epfl.ch [Github] [Google scholar] |
[Biography] [Open-source Codes] [Publications] [Professional Activities] [Major Awards]
Biography [back top]
I am currently a postdoctoral researcher at the Integrated Systems Laboratory (LSI) of EPFL. I am fortunate to work with Prof. Giovanni De Micheli. I received my Ph.D. degree in 2023 from Shanghai Jiao Tong University, where I was fortunate to be advised by Prof. Weikang Qian. I study electronic design automation (EDA). My research interests lie in logic synthesis and verification for emerging computing paradigms, such as approximate computing.
Open-source Codes [back top]
- VECSEM: Verifying average errors in approximate circuits using simulation-enhanced model counting (DATE'24): Paper; Source Code
- HEDALS: Highly efficient delay-driven approximate logic synthesis (IEEE TCAD'23): Paper; Source Code
- MECALS: A maximum error checking technique for approximate logic synthesis (DATE'23): Paper; Source Code
- VECBEE: A versatile
efficiency-accuracy configurable batch error
estimation method for greedy approximate logic
synthesis (IEEE TCAD'22): Paper;
Source
Code
- ALSRAC: Approximate logic synthesis
by resubstitution with approximate care set
(DAC'20): Paper;
Source
Code
Publications [back top]
Conference Papers
| C010. Chang Meng, Hanyu Wang, Yuqi Mai, Weikang Qian✉, and Giovanni De Micheli✉
VECSEM: Verifying average errors in approximate circuits using simulation-enhanced model counting [pdf] [code] Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024. Best Paper Nomination. Acceptance Rate: 25%. |
| C009. Chang Meng, Jiajun Sun, Yuqi Mai, and Weikang Qian✉
MECALS: A maximum error checking technique for approximate logic synthesis [pdf] [code] Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023. Acceptance Rate: 25%. |
| C008. Xingyue Qian, Chang Meng, Xiaolong Shen, Junfeng Zhao, Leibin Ni, and Weikang Qian✉
High-accuracy low-power reconfigurable architectures for decomposition-based approximate lookup table [pdf] Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023. |
| C007. Chang Meng$, Xuan Wang$, Jiajun Sun, Sijun Tao, Wei Wu, Zhizhang Wu, Leibin Ni, Xiaolong Shen, Junfeng Zhao, and Weikang Qian✉ ($equal contribution)
SEALS: Sensitivity-driven efficient approximate logic synthesis [pdf] Design Automation Conference (DAC), San Francisco, CA, USA, 2022. Acceptance Rate: 23%. |
| C006. Chang Meng, Zhiyuan Xiang, Niyiqiu Liu, Yixuan Hu, Jiahao Song, Runsheng Wang, Ru Huang, and Weikang Qian✉
DALTA: A decomposition-based approximate lookup table architecture [pdf] International Conference on Computer-Aided Design (ICCAD), Munich, Germany, 2021. Acceptance Rate: 23.5%. |
| C005. Yifan Qian, Chang Meng, Yawen Zhang, Weikang Qian✉, Runsheng Wang, and Ru Huang
Approximate logic synthesis in the loop for designing low-power neural network accelerator [pdf] International Symposium on Circuits and Systems (ISCAS), Daegu, South Korea, 2021. |
| C004. Zuodong Zhang, Runsheng Wang, Zhe Zhang, Ru Huang, Chang Meng, Weikang Qian, and Zhuangzhuang Zhou,
Reliability-enhanced circuit design flow based on approximate logic synthesis [pdf] Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, 2020. |
| C003. Chang Meng, Weikang Qian✉, and Alan Mishchenko
ALSRAC: Approximate logic synthesis by resubstitution with approximate care set [pdf] [code] Design Automation Conference (DAC), San Francisco, CA, USA, 2020. Acceptance Rate: 23.2%. |
| C002. Chang Meng, Paul Weng, Sanbao Su, and Weikang Qian✉
Advanced ordering search for multi-level approximate logic synthesis [pdf] International Workshop on Logic and Synthesis (IWLS), Lausanne, Switzerland, 2019. |
| C001. Zhuangzhuang Zhou, Yue Yao, Shuyang Huang, Sanbao Su, Chang Meng, and Weikang Qian✉
DALS: Delay-driven approximate logic synthesis [pdf] International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, 2018. |
Journal Papers
| J002. Chang Meng, Zhuangzhuang Zhou, Yue Yao, Shuyang Huang, Yuhang Chen, and Weikang Qian✉
HEDALS: Highly efficient delay-driven approximate logic synthesis [pdf] [code] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. |
| J001. Sanbao Su$, Chang Meng$, Fan Yang, Xiaolong Shen, Leibin Ni, Wei Wu, Zhihang Wu, Junfeng Zhao, and Weikang Qian✉ ($equal contribution)
VECBEE: A versatile efficiency-accuracy configurable batch error estimation method for greedy approximate logic synthesis [pdf] [code] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. |
Professional Activities [back top]
- TPC Member: GLSVLSI'24
- Conference & Journal Reviewer: DATE, ICCAD, GLSVLSI, TCAD, TVLSI, TCAS-I, TNANO, Integration
- Teaching Assistant: Computer-Aided Design of Integrated Circuits, Technical Communication
- Student Research Mentoring: 10 undergraduate students
Major Awards [back top]
- Best Paper Nomination, DATE, 2024
- Best Ph.D. dissertation award, China EDA Ecosystem Development Accelerator, 2023
- Merit student of Shanghai Jiao Tong University, 2021
- Attend A. Richard Newton Young Student Fellow Program, 2020
- Ph.D. Student Scholarship, Shanghai Jiao Tong University, 2020
- Runner-up of the International Workshop on Logic Synthesis (IWLS) Programming Contest, 2019
- National Scholarship (B.S.), 2015